1. Field of Invention
The present invention relates to a semiconductor process, and more particularly to a method of forming target patterns.
2. Description of Related Art
MOS is a basic structure widely applied to various semiconductor devices, such as memory devices, image sensors and display devices. The traditional MOS transistor is difficult to scale down due to the limitation of the fabricating process, and a multi-gate transistor with better properties is therefore developed. One example is the fin-type field effect transistor (FinFET) with multiple three-dimensional (3D) fins.
In a typical FinFET process, a thick dummy gate layer is formed on a substrate and a chemical mechanical polishing (CMP) step is performed to make the dummy gate layer flat. However, during the CMP step, the loading effect is serious due to the bad topography caused by the fin structure, so the thickness variation of the dummy gate layer within die or wafer is up to about 80 angstroms. Therefore, dummy gates are subsequently formed with uneven thicknesses. Such variation in thickness is undesirable and may affect the removal efficiency of the dummy gates, thereby deteriorating the performance of the metal-gate device.